The present invention relates generally to a clock generator, and more specifically, to a clock generation circuit for a semiconductor integrated circuit device including an information processing system in which logic operations are carried out based upon the clock.
In information processing systems where logic operations are performed in response to clocks, it is important to supervise clock timings so as to prevent erroneous operations in an internal logic operation and to realize a high-speed logic operation. In particular, in case that there are employed a plurality of information processing sections it is preferable to synchronize the clocks for the respective information processing sections in order that data transfers are surely performed at a high speed between the plural information processing sections. Such a conventional information processing system has been discussed, for instance, in ISSCC '89 Digest of Technical papers 124-125 (1989) or U.S. patent application Ser. No. 184,782 field on Apr. 22, 1988 and entitled "Information processor and information processing system utilizing clock signal" (assigned to the same assignee with the present invention and still pending). As a clock generating circuit for satisfying such a demand, it was proposed in JP-A-55-80137 (corresponding to U.S. Pat. No. 4,419,739) which discloses a circuit for generating a clock synchronized with an external signal. IEEE JOURNAL OF SOLID-STATE CIRCUITS SC-22 No. 2 (1987) pages 255 to 261, and JP-A-58-184626 show examples of clock generating circuit employing a phase-locked loop (simply referred to as a "PLL").
FIG. 2 is a schematic block diagram of a clock generating circuit employing such a PLL, as disclosed in U.S. Pat. No. 5,133,064, issued on Jul. 21, 1992. A clock generating circuit 10 is formed of a phase detector 11, a low-pass filter (LPF) 12, a voltage controlled oscillator (VCO) 13, and a frequency divider 14. The phase detector 11 continuously compares the phase difference between a timing signal related to an external signal and a synchronization clock signal. The output produced by the phase difference is smoothed by LPF 12 and supplied as a control signal for VCO 13. VCO 13 increases/decreases an oscillating frequency in response to the supplied output from LPF 12, an oscillating output is frequency-divided by a frequency divider 14 and then is outputted as a synchronization clock signal. These circuits constitute a feedback system. When the phase of the timing signal leads from the phase of the synchronization clock signal, the phase detector 11 detects the phase difference therebetween and causes the oscillating frequency of VCO 13 to increase via LPF 12. When the oscillating frequency of VCO 13 is increased, the frequency of the synchronization clock signal is also increased so that the phase of the synchronization clock signal leads and the phase difference between the synchronization clock signal and the timing signal is decreased. Conversely, in situations where the phase of the timing signal is delayed from the phase of the synchronization clock signal, the phase of the synchronization clock signal is delayed, so that the phase difference between the timing signal and synchronization clock signal is made smaller. In other words, PLL 10 operates to synchronize the phase of the synchronization clock signal with that of the timing signal and also to make both frequencies coincident, which functions as an automatic frequency control.
Various circuits 11 to 14 have been hitherto proposed as circuit elements forming PLL 10, which are selectively utilized taking account of a desired overall performance. For example, Japanese Patent Application No. 58-237228 (JP-A-60-128709). In general, as to VCO 13, a capacitor (e.g., a stray capacitance) is employed therein, a charging/discharging current thereof is controlled in response to an input voltage, whereby a time constant is varied so as to determine the oscillating frequency. However, there is such a limitation that the charging/discharging current of the capacitor may be varied within a predetermined range. As a result, a variable range of the oscillating frequency is necessarily restricted to a predetermined range.
The following is a detailed description of why such a limitation is given.
Since PLL 10 is so operated as to make the phase of the timing signal coincident with that of the synchronization clock signal, there is a case where the phase of the timing signal is coincident with that of the synchronization clock signal even when the frequency of the synchronization clock signal is equal to a frequency produced by multiplying the frequency of the timing signal by an integral number or an inverse number. In this case, since there is no phase difference between these signals, PLL 10 is brought into a balanced condition, and thus a quasi phase-locked state may occur. To avoid this difficulty, the oscillating frequency of VCO 13 employed in PLL 10 must be limited to a predetermined range over which no quasi phase-locked state occurs. If the oscillating frequency range of VCO 13 is wide, the variations in the oscillating frequency with respect to those in the input voltage become large so that the loop gain of PLL 10 becomes large. Since the noise bandwidth of PLL 10 becomes high when the loop gain of PLL 10 becomes large, the operation of PLL 10 becomes unstable. Under such circumstances, in general, the variable range of the oscillating frequency of VCO 13 is set to a predetermined range.
Now, an explanation is made of the above-mentioned problems in the art. In PLL 10 represented in FIG. 2, both the phase and frequency of the timing signal are coincident with those of the synchronization clock signal by way of the feedback system formed of the respective circuit elements 11 to 14. However, as above mentioned, the frequency of the synchronization clock signal depends upon the oscillating frequency of VCO 13, and therefore cannot be varied within a range corresponding to the oscillating frequency range of VCO 13. As a consequence, in the case where the frequency of the timing frequency exceeds over the frequency range of the synchronized clock signal corresponding to the oscillating frequency range of VCO 13, PLL 10 is no longer operated. There is a problem that the synchronization of the clock signals between the information processing sections cannot be maintained.
By the way, it is often required to maintain the synchronization of such a clock signal even with the application of an input timing signal frequency exceeding over the frequency range of a synchronized clock signal. In an information processing system such as computer or minicomputer, each of the information processing sections employed in the system is operated at a high speed. Recently, in an information processing section such as a processor or a controller fabricated by a semiconductor integrated circuit utilizing CMOS techniques, the semiconductor integrated circuit can be operated at the clock frequency of 30 MHz. Moreover, a report has been made that such a circuit is operable at the frequency higher than 70 MHz by utilizing Bi CMOS techniques. Then, these semiconductor integrated circuits are not only operated at the maximum frequency, but also operated even at a frequency lower than this maximum frequency. In other words, when tests are performed to manufacturing steps of such semiconductor integrated circuits, a diagnostic circuit additionally provided for the testing purpose must operate at a frequency, for instance, which is several MHz lower than the usual operation frequency of the normal logic circuits. Namely it is desired that clock generating circuits included in respective information processing systems are preferably operable under the input or timing clock frequencies from several MHz to several tens MHz.
In case that the input clock frequency range of the clock generating circuit is narrow, there is a possibility of incapability of the desired operation of the clock generating circuit when the operating frequency must be varied due to the testing operation. As a consequence, it is required to additionally employ an exclusive clock generating circuit in response to such a variable frequency range of the input timing frequency. Otherwise, means for externally adjusting the operating range of the clock generating circuit must be provided, and the adjustments must be made for every circuit in correspondence with the desired frequencies.